1. Field of the Invention
The present invention relates to semiconductor memories and, more particularly, to semiconductor memories having redundant rows and/or columns used to increase yield rates in the manufacture and use of semiconductor memories.
2. Statement of the Problem
A problem exists in manufacturing semiconductor memories in that certain rows or columns in the semiconductor memory may contain defective memory cells. A need exists for a redundancy design to provide redundant rows and columns in order to increase the manufacturing yield of such semiconductor memories in order to lower the overall cost of manufacturing such memory devices. Hence, upon completion of manufacturing, the memory chip is tested for such defects and in the presence of such defects, the defective columns and rows are avoided and redundant columns and rows are utilized. A number of conventional approaches are available for providing such column and row redundancy in the manufacture of semiconductor memories.
Semiconductor memories can also fail in the field at, for example, a customer's location. A further need, therefore, exists to test the semiconductor memory in the field without the use of field personnel or special equipment. In the presence of such field failures, the redundant memory rows and columns should be configured in to correct for such memory field errors.
A final combined need exists to provide programmable steering logic to control the routing of signals from defective rows/columns into the good, redundant rows/columns not only at the point of manufacturing, but also upon each system start-up even though already configured when manufactured.
3. Results of the Patentability Search
A patentability search directed to the above problem was conducted with the following patents being uncovered:
______________________________________ PAT. NO. INVENTOR ISSUE DATE ______________________________________ 3,654,610 Sander et al. Apr. 4, 1972 3,940,740 Coontz Feb. 24, 1976 4,691,301 Anderson Sep. 1, 1987 4,754,434 Wang et al. Jun. 28, 1988 4,768,193 Takemae Aug. 30, 1988 4,951,253 Sahara et al. Aug. 21, 1990 ______________________________________
U.S. Pat. No. 4,951,253 sets forth a semiconductor memory system having a redundant column used for replacing defective column. The '253 approach provides a redundant column specifically designed for use for semiconductor memory systems of the serial column access type. The '253 approach requires an address counter for monitoring the address data, a defective address detection circuit for detecting a defective address, and a redundant column selection circuit for selecting the redundant column at the time of a defective address. The redundant data selection circuit switches the data line connecting the data input/output drive circuit from the regular data lines to the redundant data lines. For operation, internal fuses are selectively blown off, at the point of manufacture, for the defective columns. The blowing of the fuse provides the necessary signal potential to program for the redundancy. Hence, the '253 approach requires a blown fuse to generate the address of a defective column in order to select the redundant column and, hence, this approach requires special equipment and is not suitable for "in the field" failures of the memory.
U.S. Pat. No. 3,654,610 sets forth a memory system including at least one redundant row of storage cells and at least one redundant column of storage cells. A code converter is embodied for converting the binary addresses of each of the rows and columns of the memory to combinatorial addresses. Additional combinatorial addresses are associated with the defective rows or columns. The '610 approach requires re-routing of wires to eliminate the bad lines and to substitute for the good lines or by providing proper logic in the necessary code converter circuit. Again, the '610 approach is designed for the manufacturing of semiconductor memories and is not adaptable for "field failures."
U.S. Pat. No. 4,768,193 pertains to a semiconductor memory device having error correction and incorporating a redundancy configuration. The '193 patent also requires the use of inhibit circuits or fuses which are selectively blown when a defective row or column is detected at the point of manufacture. In one embodiment, the inhibit circuit comprises switch circuits for receiving signals so that when the signal received is high (corresponding to a defective cell) the corresponding switch is shut off so that the data read from the defective cell is forcibly made "0."
U.S. Pat. No. 4,754,434 sets forth an apparatus for selecting redundant rows of memory cells wherein the addressing of a defective row of memory cells coupled to a first set of bit lines results in the selection of a redundant row of memory cells coupled to a second set of bit lines. The '434 approach utilizes an indirect fusing technique. The fuses are selectively blown based upon bit lines.
U.S. Pat. No. 4,691,301 also sets forth a semiconductor memory with redundant column circuitry. The '301 patent utilizes a fuse which is selectively blown at manufacturing to activate a single pole double throw switch which permits switching of the defective column out of the memory. The switch interconnects the adjacent good column in substitution for the defective column and all of the other adjacent columns are pushed over so that the last column is pushed over onto the redundant column.
U.S. Pat. No. 3,940,740 pertains to a fabricating process for increasing the yield of a micro electronic memory device by providing additional rows and columns. The '740 process tests the memory at the point of manufacture and electrically alters the memory configuration to by-pass defects. The '740 patent utilizes a series of fusible links to accomplish this.
All of the above prior art approaches uncovered in the patentability search provide redundant columns or rows or both in order to increase the manufacturing yield of semiconductor memories. None of the above approaches are suitable for "in field" detection of defective row/columns or for reconfiguration in the field since special equipment is required to "blow" the fusible links. Hence, a need exists for a circuit arrangement which utilizes redundant rows and columns that does not require physical permanent alterations such as by "blowing" fuses. Rather, a need exists to provide column and row redundancy that is easily programmed at the point of manufacturing, at the point of use in the field and with the ability to continually test the memory for new defects and to then reconfigure the memory even though priorly reconfigured around old defects. Furthermore, the circuitry for providing the redundancy should be also simple in design so as not to interfere with the speed and processing capabilities of the semiconductor memory.
Of the patents uncovered in the patentability search, the '740 and the '301 patents are most pertinent to the teachings of the present invention. The '740 patent provides a redundancy scheme for a global redundant row and/or column in the memory array. This redundant row/column can be enabled in lieu of the defective row/column. The disadvantage of the '740 technique is that the defective row/column is actually shifted to the global redundant row/column thereby encountering a performance problem.
The '301 patent unlike the '740 patent shifts the row/column control around the defective row/column by pushing columns adjacent the defective column to the redundant column. The '301 approach requires the blowing of a fuse to activate the switch in order to perform the pushing. A need exists to eliminate the requirement of a fuse and to make the redundant row/column selection and reconfiguration fully programmable so as to be utilized in the field upon, for example, system start-up.
4. Solution to the Problem
The present invention provides a solution to the above problem by providing a fully programmable switched row/column memory redundancy circuit for semiconductor memories. The redundancy circuit of the present invention can be programmed either at the point of manufacture or subsequently in the field so as to continually test and reconfigure the memory array to avoid defective rows or columns through use of redundant rows or columns. Unlike prior approaches, the present invention is fully digital and does not require blowing fuses to enable the redundancy reconfiguration. Indeed, once configured, to overcome a current defect, the redundancy circuit of the present invention can be subsequently reconfigured in the event that a future defect occurs. Additionally, the present invention orients the switches in a given direction so that unlike the approach in the '301 patent, additional decode circuitry is not required. This results in a simple redundancy circuit without the need for complex combinatorial logic or decode circuits and in the ability to provide reprogrammability to correct for future field failures in addition to manufacturing defects.